For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. Optimizing the performance of each device becomes increasingly significant.
Non-volatile semiconductor memories may use stacked floating gate type field-effect-transistors. In such transistors, electrons may be injected into a floating gate of a memory cell to be programmed by biasing a control gate and grounding a body region of a substrate on which the memory cell is formed. An oxide-nitride-oxide (ONO) stack may be used as either a charge storing layer, as in a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) transistor, or as an isolation layer between the floating gate and control gate, as in a split gate flash transistor.